1. Field of the Invention
The present invention relates to a test circuit, and more particularly, to a test circuit that receives test results from a plurality of test target circuits.
2. Description of Related Art
In recent years, an increasing number of functions are implemented in a single application specific integrated circuit (ASIC). Thus, the number of circuit blocks and the size of the ASIC have been increased. To test such a large number of circuit blocks, the ASIC typically includes a test circuit having a scan chain circuit mounted therein. The use of the scan chain circuit enables testing of a large number of circuit blocks with a small number of terminals.
When a circuit block is added subsequently, however, the added block may be excluded from test targets of the scan chain circuit. In this case, it is necessary to separately provide a terminal for the added circuit block, which causes a problem of an increase in the number of terminals of the ASIC. In this regard, Japanese Unexamined Patent Application Publication No. 2006-119023 discloses a method of testing a circuit block excluded from test targets of a scan chain circuit without increasing the number of terminals.
Japanese Unexamined Patent Application Publication No. 2006-119023 discloses a technique in which a micro processing unit (MPU) mounted on the ASIC tests the circuit block excluded from the test targets of the scan chain circuit and receives the test results. According to the technique disclosed in Japanese Unexamined Patent Application Publication No. 2006-119023, the circuit block excluded from the test targets of the scan chain circuit can be tested without increasing the number of terminals.